LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;


entity latch4bits is
port(
  ck:  in std_logic;
	e:   in std_logic; 
  entrada : in std_logic_vector(3 downto 0);
  salida  : out std_logic_vector(3 downto 0)
 	);
end;

architecture alatch4bits of latch4bits is
	--signal d0,d1,d2,d3: std_logic;
	--signal q0_s,q1_s,q2_s,q3_s: std_logic;
	
	component ffd
		port(
  clr: in std_logic;
  ck:  in std_logic;
  d:   in std_logic;
  e:   in std_logic;
  q:   out std_logic;
  nq:  out std_logic 
		);
	end component;
	
begin
	ffd0: ffd port map ( '0',ck,entrada(0),e,salida(0),open);
	ffd1: ffd port map ( '0',ck,entrada(1),e,salida(1),open);
	ffd2: ffd port map ( '0',ck,entrada(2),e,salida(2),open);
	ffd3: ffd port map ( '0',ck,entrada(3),e,salida(3),open);
	
end ;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;


entity testlatch4bits is
end;

architecture atestlatch4bits of testlatch4bits is
component latch4bits is
port(
  ck:  in std_logic;
	e:   in std_logic; 
	entrada : in std_logic_vector(3 downto 0);
	salida  : out std_logic_vector(3 downto 0)
  
	
 	);
end component;

  
  signal ck_s: std_logic:='0';
  signal e_s: std_logic:='1';
  signal q_s: std_logic_vector(3 downto 0);
  signal d_s: std_logic_vector(3 downto 0);
  
begin
  
ck_s <= not ck_s after 10 ns;
e_s <= '0','1' after 400 ns,'0' after 600 ns;
d_s <= "0011","1010" after 200 ns,"1111" after 400 ns,"1110" after 601 ns;
latch4bits1 : latch4bits port map (ck_s ,e_s, q_s, d_s);   
end;

